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 HMU16/883
April 1997
16 x 16-Bit CMOS Parallel Multiplier
Description
The HMU16/883 is a high speed, low power CMOS 16 x 16-bit parallel multiplier ideal for fast, real time digital signal processing applications. The 16-bit X and Y operands may be independently specified as either two's complement or unsigned magnitude format, thereby, allowing mixed mode multiplication operations. Additional inputs are provided to accommodate format adjustment and rounding of the 32-bit product. The Format Adjust control allows the user to select a 31-bit product with the sign bit replicated in the LSP. The round control provides for rounding the most significant portion of the result by adding one to the most significant bit of the LSP. Two 16-bit Output Registers (MSP and LSP) are provided to hold the most and least significant portions of the result, respectively. These registers may be made transparent for asynchronous operation through the use of the Feedthrough Control (FT). The two halves of the product may be routed to a single 16-bit three-state output port via the output multiplexer control, and in addition, the LSP is connected to the Yinput port through a separate three-state buffer. The HMU16/883 utilizes independent clock signals (CLKX, CLKY, CLKL, CLKM) to latch the input operands and output Product Registers. This configuration maximizes throughput and simplifies bus interfacing. All outputs of the HMU16/883 also offer three-state control for multiplexing onto multi-use system busses.
Features
* This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. * 16 x 16-Bit Parallel Multiplier with Full 32-Bit Product * High-Speed (45ns) Clocked Multiply Time * Low Power CMOS Operation - ICCSB = 500A Maximum - ICCOP = 7.0mA Maximum at 1MHz * HMU16/883 is Compatible with the AM29516, LMU16, IDT7216, and the CY7C516 * Supports Two's Complement, Unsigned Magnitude and Mixed Mode Multiplication * TTL Compatible Inputs/Outputs * Three-State Outputs
Ordering Information
PART NUMBER HMU16GM-45/883 HMU16GM-60/883 TEMP. RANGE (oC) -55 to 125 -55 to 125 PACKAGE 68 Ld CPGA 68 Ld CPGA PKG. NO. N68.95 N68.95
Functional Diagram
X0-15 TCX RND TCY Y0-15/P0-15
REGISTER
REGISTER
REGISTER
OEL CLKX CLKY MULTIPLIER ARRAY
FA FT CLKM CLKL MSPSEL OEP
FORMAT ADJUST MSP REGISTER LSP REGISTER
MULTIPLEXER
P16-31/P0-15
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
2804.2
3-29
HMU16/883
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V Input or Output Voltage Applied . . . . . . . . GND -0.5V to VCC +0.5V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Information
Thermal Resistance (Typical, Note 1) JA (oC/W) JC (oC/W) CPGA Package . . . . . . . . . . . . . . . . . . 42.69 10.0 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
Operating Conditions
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4500 Gates
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. TABLE 1. HMU16/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested TEST CONDITIONS VCC = 5.5V VCC = 4.5V IOH = -400A VCC = 4.5V (Note 2) IOL = +4.0mA VCC = 4.5V (Note 2) VIN = VCC or GND VCC = 5.5V VOUT = VCC or GND VCC = 5.5V VIN = VCC or GND, VCC = 5.5V, Outputs Open f = 1.0MHz, VIN = VCC or GND VCC = 5.5V (Note 3) (Note 4) GROUP A SUBGROUPS 1, 2, 3 1, 2, 3 1, 2, 3 TEMPERATURE (oC) -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125
PARAMETER Logical One Input Voltage Logical Zero Input Voltage Output HIGH Voltage
SYMBOL VIH VIL VOH VOL II IO ICCSB
MIN 2.2 2.6
MAX 0.8 -
UNITS V V V
Output LOW Voltage
1, 2, 3
-
0.4
V
Input Leakage Current
1, 2, 3
-10
+10
mA
Output or I/O Leakage Current Standby Power Supply Current
1, 2, 3
-10
+10
mA
1, 2, 3
-
500
mA
Operating Power Supply Current
ICCOP
1, 2, 3
-55 TA 125
-
7.0
mA
Functional Test NOTES:
FT
7, 8
-55 TA 125
-
-
2. Interchanging of force and sense conditions is permitted. 3. Operating supply current is proportional to frequency, typical rating is 5mA/MHz. 4. Tested as follows: f = 1MHz, VIH (clock inputs) = 3.0, VIH (all other inputs) = 2.6, VIL = 0.4, VOH 1.5V, and VOL 1.5V.
3-30
HMU16/883
TABLE 2. HMU16/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested (NOTE 5) TEST CONDITIONS -45 GROUP A SUBGROUPS 9, 10, 11 TEMPERATURE (oC) -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 MIN MAX 70 MIN -60 MAX 90 UNITS ns
PARAMETER Unclocked Multiply Time Clocked Multiply Time X, Y, RND Setup Time Clock HIGH Pulse Width Clock LOW Pulse Width MSPSEL to Product Out Output Clock to P Output Clock to Y Three-State Enable Time Clock Low Hold Time CLKXY Relative to CLKML NOTES:
SYMBOL tMUC tMC tS tPWH tPWL tPDSEL tPDP tPDY tENA tHCL
9, 10, 11 9, 10, 11 9, 10, 11
18 15
45 -
20 20
60 -
ns ns ns
9, 10, 11 9, 10, 11
15 -
25
20 -
30
ns ns
9, 10, 11 9, 10, 11 (Note 6) 9, 10, 11
-
25 25 25
-
30 30 30
ns ns ns
(Note 7)
9, 10, 11
0
-
0
-
ns
5. AC Testing as follows: VCC = 4.5V and 5.5V. Input levels 0V and 3.0V; timing reference levels = 1.5V; output load per test load circuit, with V1 = 4V, R1 = 500 and CL = 40pF. 6. Transition is measured at 200mV from steady state voltage; output loading per test load circuit with V1 = 1.5V, R1 = 500 and CL = 40pF. 7. To ensure the correct product is entered in the Output Registers; new data may not be entered into the Input Registers before the Output Registers have been clocked.
3-31
HMU16/883
TABLE 3. HMU16/883 ELECTRICAL PERFORMANCE SPECIFICATIONS -45 PARAMETER Input Capacitance Output Capacitance I/O Capacitance X, Y, RND Hold Time Three-State Disable Time Output Rise Time Output Fall Time NOTES: 8. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design and after major process and/or design changes. 9. Guaranteed, but not 100% tested. 10. Transition is measured at 1200mV from steady state voltage; output loading per test load circuit with V1 = 1.5V, R1 = 500 and CL = 40pF. 11. Loading is as specified in the test load circuit, with V1 = 2.4V, R1 = 500 and CL = 40pF. TABLE 4. APPLICABLE SUBGROUPS CONFORMANCE GROUPS Initial Test Interim Test PDA Final Test Group A Groups C and D METHOD 100%/5004 100%/5004 100% 100% Samples/5005 SUBGROUPS 1 2, 3, 8A, 8B, 10, 11 1, 2, 3, 7, 8A, 8B, 9, 10, 11 1, 7, 9 SYMBOL CIN COUT CI/O tH tDIS tr tf From 0.8V to 2.0V From 2.0V to 0.8V CONDITIONS VCC = Open, f = 1MHz All Measurements are referenced to device GND. NOTES 1 1 1 1, 2 1, 2, 3 TEMPERATURE (oC) TA = 25 TA = 25 TA = 25 -55 TA 125 -55 TA 125 -55 TA 125 -55 TA 125 MIN 3 MAX 15 10 10 25 MIN 3 -60 MAX 15 10 10 30 UNITS pF pF pF ns ns
1, 2, 4 1, 2, 4
-
10 10
-
10 10
ns ns
3-32
HMU16/883 Burn-In Circuit
68 LEAD CPGA TOP VIEW
11 N/C X13 X15 RND TCY VCC GND MSP SEL FT OEP
10
X11
X12
X14
CLKX
TCX
VCC
GND
FA
CLKM P30/ P14 P28/ P12 P26/ P10
N/C P31/ P15 P29/ P13 P27/ P11
9
X9
X10
8
X7
X8
7
X5
X6
6
X3
X4
P24/P8 P25/P9
5
X1
X2
P22/P6 P23/P7
4
OEL
X0
P20/P4 P21/P5
3
CLKY
CLKL Y10/ P10 Y11/ P11 G Y12/ P12 Y13/ P13 H
P18/P2 P19/P3 Y14/ P14 P16/P0 P17/P1 Y15/ P15 J N/C K L
2
N/C
Y0/P0
Y2/P2 Y4/P4
Y6/P6 Y8/P8
1 A
Y1/P1 B
Y3/P3 Y5/P5 C D
Y7/P7 Y9/P9 E F
CPGA PIN B6 A6 B5 A5 B4 A4 B3 A3 B2 B1 C2 C1 D2 D1 E2 E1 F2 F1 G2 X4 X3 X2 X1 X0
PIN NAME
BURN-IN SIGNAL F6 F5 F4 F3 F2 VCC F0 F0 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 G1 H2 H1 J2 J1 K2 L2 K3 L3 K4 L4 K5 L5 K6 L6 K7 L7 K8 L8
CPGA PIN
PIN NAME Y11/P11 Y12/P12 Y13/P13 Y14/P14 Y15/P15 P0/P16 P1/P17 P2/P18 P3/P19 P4/P20 P5/P21 P6/P22 P7/P23 P8/P24 P9/P25 P10/P26 P11/P27 P12/P28 P13/P29
BURN-IN SIGNAL F13 F14 F15 F4 F5 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2
OEL CLKL CLKY Y0/P0 Y1/P1 Y2/P2 Y3/P3 Y4/P4 Y5/P5 Y6/P6 Y7/P7 Y8/P8 Y9/P9 Y10/P10
3-33
HMU16/883
CPGA PIN K9 L9 K10 K11 J10 J11 H10 H11 G10 G11 F10 F11 E10 E11 D10 D11 C10 C11 B10 A10 B9 A9 B8 A8 B7 A7 A2 K1 L10 B11 NOTES: 12. VCC = 5.5V +0.5V/-0.0V with 0.1F decoupling capacitor to GND. 13. F0 = 100kHz, F1 = F0/2, F2 = F1/2, . . . . . . . . . . . . . . . . . . . . . 14. VlH = VCC - 1V 0.5V (Min), VIL = 0.8V (Max). 15. 47k Load Resistors used on all pins except VCC and GND (PinGrid identifiers F10, G10, G11 and H11). PIN NAME P14/P30 P15/P31 CLKM OEP FA FT MSPSEL GND GND VCC VCC TCY TCX RND CLKX X15 X14 X13 X12 X11 X10 X9 X8 X7 X6 X5 N.C. N.C. N.C. N.C. BURN-IN SIGNAL VCC/2 VCC/2 F0 F1 F14 F15 F14 GND GND VCC VCC F15 F15 F1 F0 F3 F2 F15 F14 F13 F12 F11 F10 F9 F8 F7 NONE NONE NONE NONE
3-34
HMU16/883 Die Characteristics
DIE DIMENSIONS: 179 x 169 x 19 1mils METALLIZATION: Type: Si - Al or Si-Al-Cu Thickness: 8kA GLASSIVATION: Type: Nitrox Thickness: 10kA WORST CASE CURRENT DENSITY: 1.2 x 105A/cm2
Metallization Mask Layout
HMU16/883
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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